In an electronic switching system (ESS) comprising a large number of processors, use of a hierarchical processor architecture is gaining popularity. For example, an access switching subsystem performing such functions as scanning, interfacing and time switching, included in the ESS, has the hierarchical processor architecture. In the hierarchical processor architecture, the functions of processors are divided into, e.g., two hierarchies, upper and lower, wherein the upper hierarchical function is performed by main processors (MP's) and the lower hierarchical function is performed by peripheral processors (PP's).
For instance, the PP performs simple processing operations, such as supervising telephony devices, e.g., a subscriber interface device, a trunk interface device and a signaling device, and controlling system peripheral devices, e.g., a magnetic tape driver, a disk driver and a CRT (cathode-ray tube) terminal. Therefore, the scanning of the subscriber's hook-off and signal distribution function are handled by the PP. On the other hand, the MP's control a predetermined set of the PP's to perform call processing and OA&M (operation, administration and maintenance) in response to predetermined signals generated at the PP's.
As described, it is necessary to provide a data communications path between the PP and each of the devices. In the known ESS, for data transmission the PP is connected to each of the devices by using a conventional bus architecture and a predetermined bus access process. The conventional bus architecture includes lines for an address, data, a bus clock.
However, in using the conventional bus architecture, the bus clock frequency does not guarantee the speed of data transmission. In other words, the speed of data transmission between the PP and each of the devices is lower than the bus clock frequency since it takes a predetermined period of the bus clock to perform operations required at every access, such as a bus arbitration operation for the bus access and data transfer operation. For example, it takes 20 clock periods to get the bus access and transfer data when the bus clock frequency is 2.5 MHz. Therefore, for a device requiring high speed data transmission, it is necessary to increase the bus clock frequency.
At high frequencies, impedance matching is critical since the bus has the character of a transmission line. Since it is difficult to do an exact impedance matching for the bus, resulting in such a high transmission loss of the bus, the length of the bus cable is severely limited at high frequency. Subsequently, the number of the devices connected to the PP is substantially restricted.